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D a t a S h e e t , V 1 .2 , M a r c h 2 007
XC164KM
16-Bit Single-Chip Microcontroller with C166SV2 Core
Microcontrollers
Edition 2007-03 Published by Infineon Technologies AG 81726 Munich, Germany
(c) 2007 Infineon Technologies AG All Rights Reserved.
Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices, please contact the nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements, components may contain dangerous substances. For information on the types in question, please contact the nearest Infineon Technologies Office. Infineon Technologies components may be used in life-support devices or systems only with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
D a t a S h e e t , V 1 .2 , M a r c h 2 007
XC164KM
16-Bit Single-Chip Microcontroller with C166SV2 Core
Microcontrollers
XC164KM Derivatives
XC164KM Revision History: V1.2, 2007-03 Previous Version(s): V1.1, 2006-08 V1.0, 2005-11 Page 6 50 51 52 59 60 all Subjects (major changes since last revision) Design steps of the derivatives differentiated. Power consumption of the derivatives differentiated. Figure 10 adapted. Figure 12 adapted. Packages of the derivatives differentiated. Thermal resistances of the derivatives differentiated. "Preliminary" removed
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Data Sheet
V1.2, 2007-03
XC164KM Derivatives
Table of Contents
Table of Contents
1 2 2.1 3 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 4 4.1 4.2 4.3 4.3.1 4.3.2 4.3.3 5 5.1 5.2 Summary of Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 General Device Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Pin Configuration and Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Memory Subsystem and Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . Central Processing Unit (CPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . On-Chip Debug Support (OCDS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Capture/Compare Unit (CAPCOM2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General Purpose Timer (GPT12E) Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . Real Time Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Asynchronous/Synchronous Serial Interfaces (ASC0/ASC1) . . . . . . . . . . High Speed Synchronous Serial Channels (SSC0/SSC1) . . . . . . . . . . . . TwinCAN Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LXBus Controller (EBC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parallel Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Definition of Internal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . On-chip Flash Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Clock Drive XTAL1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 15 18 20 25 26 29 33 34 35 36 37 38 39 40 41 42 45 45 48 53 53 57 58
Package and Reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Flash Memory Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Data Sheet
3
V1.2, 2007-03
16-Bit Single-Chip Microcontroller with C166SV2 Core XC166 Family
XC164KM
1
Summary of Features
For a quick overview or reference, the XC164KM's properties are listed here in a condensed way. * High Performance 16-bit CPU with 5-Stage Pipeline - 25 ns Instruction Cycle Time at 40 MHz CPU Clock (Single-Cycle Execution) - 1-Cycle Multiplication (16 x 16 bit), Background Division (32 / 16 bit) in 21 Cycles - 1-Cycle Multiply-and-Accumulate (MAC) Instructions - Enhanced Boolean Bit Manipulation Facilities - Zero-Cycle Jump Execution - Additional Instructions to Support HLL and Operating Systems - Register-Based Design with Multiple Variable Register Banks - Fast Context Switching Support with Two Additional Local Register Banks - 16 Mbytes Total Linear Address Space for Code and Data - 1024 Bytes On-Chip Special Function Register Area (C166 Family Compatible) 16-Priority-Level Interrupt System with up to 63 Sources, Sample-Rate down to 50 ns 8-Channel Interrupt-Driven Single-Cycle Data Transfer Facilities via Peripheral Event Controller (PEC), 24-Bit Pointers Cover Total Address Space Clock Generation via on-chip PLL (factors 1:0.15 ... 1:10), or via Prescaler (factors 1:1 ... 60:1) On-Chip Memory Modules - 2 Kbytes On-Chip Dual-Port RAM (DPRAM) - 0/2/4 Kbytes1) On-Chip Data SRAM (DSRAM) - 2 Kbytes On-Chip Program/Data SRAM (PSRAM) - 32/64/1281) Kbytes On-Chip Program Memory (Flash Memory) On-Chip Peripheral Modules - 16-Channel General Purpose Capture/Compare Unit (CAPCOM2) - Multi-Functional General Purpose Timer Unit with 5 Timers - Two Synchronous/Asynchronous Serial Channels (USARTs) - Two High-Speed-Synchronous Serial Channels - On-Chip TwinCAN Interface (Rev. 2.0B active) with 32 Message Objects (Full CAN/Basic CAN) on Two CAN Nodes, and Gateway Functionality - On-Chip Real Time Clock, Driven by the Main Oscillator Idle, Sleep, and Power Down Modes with Flexible Power Management Programmable Watchdog Timer and Oscillator Watchdog
* * * *
*
* *
1) Depends on the respective derivative. See Table 1 "XC164KM Derivative Synopsis" on Page 6.
Data Sheet
4
V1.2, 2007-03
XC164KM Derivatives
Summary of Features * * * * * Up to 47 General Purpose I/O Lines, partly with Selectable Input Thresholds and Hysteresis On-Chip Bootstrap Loader On-Chip Debug Support via JTAG Interface 64-Pin Green LQFP Package for the -16F derivatives, 0.5 mm (19.7 mil) pitch (RoHS compliant) 64-Pin TQFP Package for the -4F/8F derivatives, 0.5 mm (19.7 mil) pitch (RoHS compliant)
Ordering Information The ordering code for Infineon microcontrollers provides an exact reference to the required product. This ordering code identifies: * * the derivative itself, i.e. its function set, the temperature range, and the supply voltage the package and the type of delivery.
For the available ordering codes for the XC164KM please refer to your responsible sales representative or your local distributor. This document describes several derivatives of the XC164KM group. Table 1 enumerates these derivatives and summarizes the differences. As this document refers to all of these derivatives, some descriptions may not apply to a specific product. For simplicity all versions are referred to by the term XC164KM throughout this document.
Data Sheet
5
V1.2, 2007-03
XC164KM Derivatives
Summary of Features Table 1 Derivative1) SAF-XC164KM-16F40F SAF-XC164KM-16F20F SAF-XC164KM-8F40F SAF-XC164KM-8F20F SAF-XC164KM-4F40F SAF-XC164KM-4F20F XC164KM Derivative Synopsis Temp. Range -40 to 85 C -40 to 85 C -40 to 85 C Program Memory On-Chip RAM Interfaces ASC0, ASC1, SSC0, SSC1, CAN0, CAN1 ASC0, ASC1, SSC0, SSC1, CAN0, CAN1 ASC0, ASC1, SSC0, SSC1, CAN0, CAN1
128 Kbytes 2 Kbytes DPRAM, Flash 4 Kbytes DSRAM, 2 Kbytes PSRAM 64 Kbytes Flash 32 Kbytes Flash 2 Kbytes DPRAM, 2 Kbytes DSRAM, 2 Kbytes PSRAM 2 Kbytes DPRAM, 2 Kbytes PSRAM
1) This Data Sheet is valid for: devices starting with and including design step BA for the -16F derivatives, and for devices starting with and including design step AA for -4F/8F derivatives.
Data Sheet
6
V1.2, 2007-03
XC164KM Derivatives
General Device Information
2
General Device Information
The XC164KM derivatives are high-performance members of the Infineon XC166 Family of full featured single-chip CMOS microcontrollers. These devices extend the functionality and performance of the C166 Family in terms of instructions (MAC unit), peripherals, and speed. They combine high CPU performance (up to 40 million instructions per second) with high peripheral functionality and enhanced IO-capabilities. They also provide clock generation via PLL and various on-chip memory modules such as program Flash, program RAM, and data RAM.
VDDI/P
VSS
PORT1 14 bit
XTAL1 XTAL2 NMI RSTIN Port 5 14 bit XC164KM
Port 3 15 bit Port 9 6 bit TRST
MCA05554_XC164KM
Figure 1
Logic Symbol
Data Sheet
7
V1.2, 2007-03
XC164KM Derivatives
General Device Information
2.1
Pin Configuration and Definition
The pins of the XC164KM are described in detail in Table 2, including all their alternate functions. Figure 2 summarizes all pins in a condensed way, showing their location on the 4 sides of the package. E* marks pins to be used as alternate external interrupt inputs.
P1H.0/EX0IN/CC23IO P1H.1/EX1IN/MRST1 P1H.2/EX2IN/MTRS1 P1H.3/EX3IN/T7IN/SCLK1 P1H.4/CC24IO/EX4IN P1H.5/CC25IO/EX5IN VSS V DDP P5.0 P5.1 P5.2 P5.3 P5.4 P5.5 P5.10/T6EUD P5.11/T5EUD
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 1 48 47 2 46 3 4 45 44 5 6 43 7 42 8 41 9 40 10 39 38 11 12 37 13 36 14 35 15 34 16 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
NMI RSTIN TRST XTAL2 XTAL1 V SS V DDI V DDP P1L.7/CC22IO P1L.6 P1L.5 P1L.4 P1L.3 P1L.2 P1L.1 P1L.0
XC164KM
P9.5/CC21IO P9.4/CC20IO P9.3/CC19IO/CAN1_TxD P9.2/CC18IO/CAN1_RxD/E* P9.1/CC17IO/CAN2_TxD P9.0/CC16IO/CAN2_RxD/E* P3.15/CLKOUT/FOUT V SS V DDP P3.13/SCLK0/E* P3.11/RxD0/E* P3.10/TxD0/E* P3.9/MTSR0 P3.8/MRST0 P3.7/T2IN/BRKIN P3.6/T3IN
P5.6 P5.7 V SS V SS P5.12/T6IN P5.13/T5IN P5.14/T4EUD P5.15/T2EUD V SS V DDI VD DP P3.1/T6OUT/RxD1/TCK/E* P3.2/CAPIN/TDI P3.3/T3OUT /TDO P3.4/T3EUD/TMS P3.5/T4IN/TxD1/BRKOUT
mc_xc164km_pinout.vsd
Figure 2
Pin Configuration (top view)
Data Sheet
8
V1.2, 2007-03
XC164KM Derivatives
General Device Information Table 2 Symbol RSTIN Pin Definitions and Functions Pin Num. 63 Input Function Outp. I Reset Input with Schmitt-Trigger characteristics. A low-level at this pin while the oscillator is running resets the XC164KM. A spike filter suppresses input pulses < 10 ns. Input pulses > 100 ns safely pass the filter. The minimum duration for a safe recognition should be 100 ns + 2 CPU clock cycles. Note: The reset duration must be sufficient to let the hardware configuration signals settle. External circuitry must guarantee low-level at the RSTIN pin at least until both power supply voltages have reached the operating range. NMI 64 I Non-Maskable Interrupt Input. A high to low transition at this pin causes the CPU to vector to the NMI trap routine. When the PWRDN (power down) instruction is executed, the NMI pin must be low in order to force the XC164KM into power down mode. If NMI is high, when PWRDN is executed, the part will continue to run in normal mode. If not used, pin NMI should be pulled high externally. Port 9 is a 6-bit bidirectional I/O port. Each pin can be programmed for input (output driver in high-impedance state) or output (configurable as push/pull or open drain driver). The input threshold of Port 9 is selectable (standard or special). The following Port 9 pins also serve for alternate functions: CC16IO: (CAPCOM2) CC16 Capture Inp./Compare Outp., CAN2_RxD: (CAN Node 2) Receive Data Input1), EX5IN: (Fast External Interrupt 5) Input (alternate pin A) CC17IO: (CAPCOM2) CC17 Capture Inp./Compare Outp., CAN2_TxD: (CAN Node 2) Transmit Data Output, CC18IO: (CAPCOM2) CC18 Capture Inp./Compare Outp., CAN1_RxD: (CAN Node 1) Receive Data Input1), EX4IN: (Fast External Interrupt 4) Input (alternate pin A) CC19IO: (CAPCOM2) CC19 Capture Inp./Compare Outp., CAN1_TxD: (CAN Node 1) Transmit Data Output, CC20IO: (CAPCOM2) CC20 Capture Inp./Compare Outp. CC21IO: (CAPCOM2) CC21 Capture Inp./Compare Outp. Note: At the end of an external reset P9.4 and P9.5 also may input startup configuration values.
Port 9
43-48
IO
P9.0
43
P9.1 P9.2
44 45
P9.3 P9.4 P9.5
46 47 48
I/O I I I/O O I/O I I I/O O I/O I/O
Data Sheet
9
V1.2, 2007-03
XC164KM Derivatives
General Device Information Table 2 Symbol Port 5 P5.10 P5.11 P5.12 P5.13 P5.14 P5.15 TRST Pin Definitions and Functions (cont'd) Pin Num. 9-18, 21-24 15 16 21 22 23 24 62 Input Function Outp. I I I I I I I I Port 5 is a 14-bit input-only port. Some pins of Port 5 also serve as timer inputs: T6EUD: GPT2 Timer T6 Ext. Up/Down Control Input T5EUD: GPT2 Timer T5 Ext. Up/Down Control Input T6IN: GPT2 Timer T6 Count/Gate Input T5IN: GPT2 Timer T5 Count/Gate Input T4EUD: GPT1 Timer T4 Ext. Up/Down Control Input T2EUD: GPT1 Timer T2 Ext. Up/Down Control Input Test-System Reset Input. For normal system operation, pin TRST should be held low. A high level at this pin at the rising edge of RSTIN enables the hardware configuration and activates the XC164KM's debug system. In this case, pin TRST must be driven low once to reset the debug system.
Data Sheet
10
V1.2, 2007-03
XC164KM Derivatives
General Device Information Table 2 Symbol Port 3 Pin Definitions and Functions (cont'd) Pin Num. Input Function Outp. Port 3 is a 13-bit bidirectional I/O port. Each pin can be programmed for input (output driver in high-impedance state) or output (configurable as push/pull or open drain driver). The input threshold of Port 3 is selectable (standard or special).The following Port 3 pins also serve for alternate functions: T6OUT: [GPT2] Timer T6 Toggle Latch Output, RxD1: [ASC1] Data Input (Async.) or Inp./Outp. (Sync.), EX1IN: [Fast External Interrupt 1] Input (alternate pin A), TCK: [Debug System] JTAG Clock Input CAPIN: [GPT2] Register CAPREL Capture Input, TDI: [Debug System] JTAG Data In T3OUT: [GPT1] Timer T3 Toggle Latch Output, TDO: [Debug System] JTAG Data Out T3EUD: [GPT1] Timer T3 External Up/Down Control Input, TMS: [Debug System] JTAG Test Mode Selection T4IN: [GPT1] Timer T4 Count/Gate/Reload/Capture Inp. TxD1: [ASC0] Clock/Data Output (Async./Sync.), BRKOUT: [Debug System] Break Out T3IN: [GPT1] Timer T3 Count/Gate Input T2IN: [GPT1] Timer T2 Count/Gate/Reload/Capture Inp. BRKIN: [Debug System] Break In MRST0: [SSC0] Master-Receive/Slave-Transmit In/Out. MTSR0: [SSC0] Master-Transmit/Slave-Receive Out/In. TxD0: [ASC0] Clock/Data Output (Async./Sync.), EX2IN: [Fast External Interrupt 2] Input (alternate pin B) RxD0: [ASC0] Data Input (Async.) or Inp./Outp. (Sync.), EX2IN: [Fast External Interrupt 2] Input (alternate pin A) SCLK0: [SSC0] Master Clock Output / Slave Clock Input., EX3IN: [Fast External Interrupt 3] Input (alternate pin A) CLKOUT: System Clock Output (= CPU Clock), FOUT: Programmable Frequency Output
28-39, IO 42
P3.1
28
P3.2 P3.3 P3.4 P3.5
29 30 31 32
P3.6 P3.7 P3.8 P3.9 P3.10 P3.11 P3.13 P3.15
33 34 35 36 37 38 39 42
O I/O I I I I O O I I I O O I I I I/O I/O O I I/O I I/O I O O
Data Sheet
11
V1.2, 2007-03
XC164KM Derivatives
General Device Information Table 2 Symbol Pin Definitions and Functions (cont'd) Pin Num. Input Function Outp. IO PORT1 consists of one 8-bit and one 6-bit bidirectional I/O port P1L and P1H. Each pin can be programmed for input (output driver in high-impedance state) or output. The following PORT1 pins also serve for alt. functions: CC22IO: [CAPCOM2] CC22 Capture Inp./Compare Outp. EX0IN: [Fast External Interrupt 0] Input (default pin), CC23IO: [CAPCOM2] CC23 Capture Inp./Compare Outp. EX1IN: [Fast External Interrupt 1] Input (default pin), MRST1: [SSC1] Master-Receive/Slave-Transmit In/Out. EX2IN: [Fast External Interrupt 2] Input (default pin), MTSR1: [SSC1] Master-Transmit/Slave-Receive Out/Inp. T7IN: [CAPCOM2] Timer T7 Count Input, SCLK1: [SSC1] Master Clock Output / Slave Clock Input, EX3IN: [Fast External Interrupt 3] Input (default pin), CC24IO: [CAPCOM2] CC24 Capture Inp./Compare Outp., EX4IN: [Fast External Interrupt 4] Input (default pin) CC25IO: [CAPCOM2] CC25 Capture Inp./Compare Outp., EX5IN: [Fast External Interrupt 5] Input (default pin) Note: At the end of an external reset P1H.4 and P1H.5 also may input startup configuration values XTAL2 XTAL1 61 60 O I XTAL2: Output of the oscillator amplifier circuit XTAL1: Input to the oscillator amplifier and input to the internal clock generator To clock the device from an external source, drive XTAL1, while leaving XTAL2 unconnected. Minimum and maximum high/low and rise/fall times specified in the AC Characteristics must be observed. Note: Input pin XTAL1 belongs to the core voltage domain. Therefore, input voltages must be within the range defined for VDDI.
PORT1 1-6, 49-56
P1L.7 P1H.0 P1H.1 P1H.2 P1H.3
56 1 2 3 3
P1H.4 P1H.5
5 6
I/O I I/O I I/O I I/O I I/O I I/O I I/O I
VDDI
26, 58 -
Digital Core Supply Voltage (On-Chip Modules): +2.5 V during normal operation and idle mode. Please refer to the Operating Condition Parameters
Data Sheet
12
V1.2, 2007-03
XC164KM Derivatives
General Device Information Table 2 Symbol Pin Definitions and Functions (cont'd) Pin Num. Input Function Outp. Digital Pad Supply Voltage (Pin Output Drivers): +5 V during normal operation and idle mode. Please refer to the Operating Condition Parameters Digital Ground Connect decoupling capacitors to adjacent VDD/VSS pin pairs as close as possible to the pins. All VSS pins must be connected to the ground-line or groundplane.
VDDP VSS
8, 27, - 40, 57 7, 25, - 41, 59
1) The CAN interface lines are assigned to port P9 under software control.
Data Sheet
13
V1.2, 2007-03
XC164KM Derivatives
Functional Description
3
Functional Description
The architecture of the XC164KM combines advantages of RISC, CISC, and DSP processors with an advanced peripheral subsystem in a very well-balanced way. In addition, the on-chip memory blocks allow the design of compact systems-on-silicon with maximum performance (computing, control, communication). The on-chip memory blocks (program code-memory and SRAM, dual-port RAM, data SRAM) and the set of generic peripherals are connected to the CPU via separate buses. Another bus, the LXBus, connects additional on-chip resources (see Figure 3). This bus structure enhances the overall system performance by enabling the concurrent operation of several subsystems of the XC164KM. The following block diagram gives an overview of the different on-chip components and of the advanced, high bandwidth internal bus structure of the XC164KM.
PSRAM
2 Kbytes
DPRAM
2 Kbytes
0/2/4 Kbytes
DSRAM
ProgMem PMU
32/64/128 Kbytes
CPU
C166SV2-Core
Debug Support
OCDS
DMU
Flash
reduced LXBus Control EBC
XTAL
Clock Generation
Osc / PLL
RTC WDT
Interrupt & PEC
Interrupt Bus
Peripheral Data Bus
GPT ASC0 ASC1 SSC0 SSC1
T2 T3 T4 T5 T6 Port 9 6 BR Gen BR Gen Port 5 14 BR Gen BR Gen Port 3 13 (U SAR T) (U SAR T) (SPI) (SPI)
CC2
T7 T8
Twin CAN
A
L XBu s
B
POR T1 14
Mc_xc164km_block1.vsd
Figure 3
Data Sheet
Block Diagram
14 V1.2, 2007-03
XC164KM Derivatives
Functional Description
3.1
Memory Subsystem and Organization
The memory space of the XC164KM is configured in a von Neumann architecture, which means that all internal and external resources, such as code memory, data memory, registers and I/O ports, are organized within the same linear address space. This common memory space includes 16 Mbytes and is arranged as 256 segments of 64 Kbytes each, where each segment consists of four data pages of 16 Kbytes each. The entire memory space can be accessed byte wise or word wise. Portions of the on-chip DPRAM and the register spaces (E/SFR) have additionally been made directly bit addressable. The internal data memory areas and the Special Function Register areas (SFR and ESFR) are mapped into segment 0, the system segment. The Program Management Unit (PMU) handles all code fetches and, therefore, controls accesses to the program memories, such as Flash memory and PSRAM. The Data Management Unit (DMU) handles all data transfers and, therefore, controls accesses to the DSRAM and the on-chip peripherals. Both units (PMU and DMU) are connected via the high-speed system bus to exchange data. This is required if operands are read from program memory, code or data is written to the PSRAM, or data is read from or written to peripherals on the LXBus (such as TwinCAN). The system bus allows concurrent two-way communication for maximum transfer performance. 32/64/128 Kbytes of on-chip Flash memory1) store code or constant data. The on-chip Flash memory is organized as four 8-Kbyte sectors and up to three 32-Kbyte sectors. Each sector can be separately write protected2), erased and programmed (in blocks of 128 Bytes). The complete Flash area can be read-protected. A password sequence temporarily unlocks protected areas. The Flash module combines very fast 64-bit onecycle read accesses with protected and efficient writing algorithms for programming and erasing. Thus, program execution out of the internal Flash results in maximum performance. Dynamic error correction provides extremely high read data security for all read accesses. Programming typically takes 2 ms per 128-byte block (5 ms max.), erasing a sector typically takes 200 ms (500 ms max.). 2 Kbytes of on-chip Program SRAM (PSRAM) are provided to store user code or data. The PSRAM is accessed via the PMU and is therefore optimized for code fetches. 0/2/4 Kbytes1) of on-chip Data SRAM (DSRAM) are provided as a storage for general user data. The DSRAM is accessed via the DMU and is therefore optimized for data accesses. DSRAM is not available in the XC164KM-4F derivatives.
1) Depends on the respective derivative. See Table 1 "XC164KM Derivative Synopsis" on Page 6. 2) Each two 8-Kbyte sectors are combined for write-protection purposes.
Data Sheet
15
V1.2, 2007-03
XC164KM Derivatives
Functional Description 2 Kbytes of on-chip Dual-Port RAM (DPRAM) are provided as a storage for user defined variables, for the system stack, general purpose register banks. A register bank can consist of up to 16 word wide (R0 to R15) and/or byte wide (RL0, RH0, ..., RL7, RH7) so-called General Purpose Registers (GPRs). The upper 256 bytes of the DPRAM are directly bit addressable. When used by a GPR, any location in the DPRAM is bit addressable. 1024 bytes (2 x 512 bytes) of the address space are reserved for the Special Function Register areas (SFR space and ESFR space). SFRs are word wide registers which are used for controlling and monitoring functions of the different on-chip units. Unused SFR addresses are reserved for future members of the XC166 Family. Therefore, they should either not be accessed, or written with zeros, to ensure upward compatibility. Table 3 XC164KM Memory Map Start Loc. FF'F000H F8'0000H E0'0800H E0'0000H C2'0000H C0'0000H C0'0000H C0'0000H Reserved TwinCAN registers Reserved SFR area Dual-Port RAM Reserved for DPRAM ESFR area XSFR area Reserved Data SRAM Reserved for DSRAM Reserved 20'0800H 20'0000H 01'0000H 00'FE00H 00'F600H 00'F200H 00'F000H 00'E000H 00'D000H 00'C000H 00'8000H 00'0000H End Loc. FF'FFFFH FF'FFFFH F7'FFFFH E0'07FFH DF'FFFFH C1'FFFFH C0'FFFFH C0'7FFFH BF'FFFFH 20'07FFH 1F'FFFFH 00'FFFFH 00'FDFFH 00'F5FFH 00'F1FFH 00'EFFFH 00'DFFFH 00'CFFFH 00'BFFFH 00'7FFFH Area Size1) 4 Kbytes 508 Kbytes 2 Kbytes < 2 Mbytes 128 Kbytes 64 Kbytes 32 Kbytes < 10 Mbytes 2 Kbytes < 2 Mbytes 0.5 Kbyte 2 Kbytes 1 Kbyte 0.5 Kbyte 4 Kbytes 6 Kbytes 4 Kbytes 16 Kbytes 32 Kbytes Notes
2)
Address Area Flash register space Reserved (Acc. trap) Reserved for PSRAM Program SRAM Reserved for pr. mem. Program Flash
- - Minus Flash XC164KM-16F XC164KM-8F XC164KM-4F Minus TwinCAN Accessed via EBC Minus segment 0 - - - - - -
3)
< 1.5 Mbytes Minus PSRAM
- -
1) The areas marked with "<" are slightly smaller than indicated, see column "Notes".
Data Sheet
16
V1.2, 2007-03
XC164KM Derivatives
Functional Description
2) Not defined register locations return a trap code (1E9BH). 3) Depends on the respective derivative. See Table 1 "XC164KM Derivative Synopsis" on Page 6.
Data Sheet
17
V1.2, 2007-03
XC164KM Derivatives
Functional Description
3.2
Central Processing Unit (CPU)
The main core of the CPU consists of a 5-stage execution pipeline with a 2-stage instruction-fetch pipeline, a 16-bit arithmetic and logic unit (ALU), a 32-bit/40-bit multiply and accumulate unit (MAC), a register-file providing three register banks, and dedicated SFRs. The ALU features a multiply and divide unit, a bit-mask generator, and a barrel shifter.
PM U CPU P refetch U nit B ranch U nit FIFO CSP CPUCON1 CPUCON2 IP VECSEG T FR Injection/ Exception Handler IFU DPP0 DPP1 DPP2 DPP3 SPSEG SP S TK O V S TK U N CP RR 15 15 RR 1415 14 R R 14 GPRs GPRs GPRs RR 1 1 RR 0 1 0R R0 RF + /MDL ONES ALU DM U B u ffer WB
2-S tage P refetch P ipeline 5-S tage P ipeline
PSRAM Flash/RO M
DPRAM
R eturn S tack QR0 QR1
IPIP
ID X 0 ID X 1 QX0 QX1
R 15 R 14 GPRs R1 R0
+ /-
+ /-
ADU
D ivisio n U n it M u ltip ly U n it B it-M a sk-G e n . B a rre l-S h ifte r
M ultiply U nit
MRW MCW MSW MAL
MDC PSW MDH ZERO S
+ /MAH M AC
DSRAM EBC Peripherals
m ca04917_x.vsd
Figure 4
CPU Block Diagram
Based on these hardware provisions, most of the XC164KM's instructions can be executed in just one machine cycle which requires 25 ns at 40 MHz CPU clock. For
Data Sheet 18 V1.2, 2007-03
XC164KM Derivatives
Functional Description example, shift and rotate instructions are always processed during one machine cycle independent of the number of bits to be shifted. Also multiplication and most MAC instructions execute in one single cycle. All multiple-cycle instructions have been optimized so that they can be executed very fast as well: for example, a 32-/16-bit division is started within 4 cycles, while the remaining 15 cycles are executed in the background. Another pipeline optimization, the branch target prediction, allows eliminating the execution time of branch instructions if the prediction was correct. The CPU has a register context consisting of up to three register banks with 16 word wide GPRs each at its disposal. One of these register banks is physically allocated within the on-chip DPRAM area. A Context Pointer (CP) register determines the base address of the active register bank to be accessed by the CPU at any time. The number of register banks is only restricted by the available internal RAM space. For easy parameter passing, a register bank may overlap others. A system stack of up to 32 Kwords is provided as a storage for temporary data. The system stack can be allocated to any location within the address space (preferably in the on-chip RAM area), and it is accessed by the CPU via the stack pointer (SP) register. Two separate SFRs, STKOV and STKUN, are implicitly compared against the stack pointer value upon each stack access for the detection of a stack overflow or underflow. The high performance offered by the hardware implementation of the CPU can efficiently be utilized by a programmer via the highly efficient XC164KM instruction set which includes the following instruction classes: * * * * * * * * * * * * * Standard Arithmetic Instructions DSP-Oriented Arithmetic Instructions Logical Instructions Boolean Bit Manipulation Instructions Compare and Loop Control Instructions Shift and Rotate Instructions Prioritize Instruction Data Movement Instructions System Stack Instructions Jump and Call Instructions Return Instructions System Control Instructions Miscellaneous Instructions
The basic instruction length is either 2 or 4 bytes. Possible operand types are bits, bytes and words. A variety of direct, indirect or immediate addressing modes are provided to specify the required operands.
Data Sheet
19
V1.2, 2007-03
XC164KM Derivatives
Functional Description
3.3
Interrupt System
With an interrupt response time of typically 8 CPU clocks (in case of internal program execution), the XC164KM is capable of reacting very fast to the occurrence of nondeterministic events. The architecture of the XC164KM supports several mechanisms for fast and flexible response to service requests that can be generated from various sources internal or external to the microcontroller. Any of these interrupt requests can be programmed to being serviced by the Interrupt Controller or by the Peripheral Event Controller (PEC). In contrast to a standard interrupt service where the current program execution is suspended and a branch to the interrupt vector table is performed, just one cycle is `stolen' from the current CPU activity to perform a PEC service. A PEC service implies a single byte or word data transfer between any two memory locations with an additional increment of either the PEC source, or the destination pointer, or both. An individual PEC transfer counter is implicitly decremented for each PEC service except when performing in the continuous transfer mode. When this counter reaches zero, a standard interrupt is performed to the corresponding source related vector location. PEC services are very well suited, for example, for supporting the transmission or reception of blocks of data. The XC164KM has 8 PEC channels each of which offers such fast interrupt-driven data transfer capabilities. A separate control register which contains an interrupt request flag, an interrupt enable flag and an interrupt priority bit field exists for each of the possible interrupt nodes. Via its related register, each node can be programmed to one of sixteen interrupt priority levels. Once having been accepted by the CPU, an interrupt service can only be interrupted by a higher prioritized service request. For the standard interrupt processing, each of the possible interrupt nodes has a dedicated vector location. Fast external interrupt inputs are provided to service external interrupts with high precision requirements. These fast interrupt inputs feature programmable edge detection (rising edge, falling edge, or both edges). Software interrupts are supported by means of the `TRAP' instruction in combination with an individual trap (interrupt) number. Table 4 shows all of the possible XC164KM interrupt sources and the corresponding hardware-related interrupt flags, vectors, vector locations and trap (interrupt) numbers. Note: Interrupt nodes which are not assigned to peripherals (unassigned nodes), may be used to generate software controlled interrupt requests by setting the respective interrupt request bit (xIR).
Data Sheet
20
V1.2, 2007-03
XC164KM Derivatives
Functional Description Table 4 XC164KM Interrupt Nodes Control Register CC1_CC8IC CC1_CC9IC CC1_CC10IC CC1_CC11IC CC1_CC12IC CC1_CC13IC CC2_CC16IC CC2_CC17IC CC2_CC18IC CC2_CC19IC CC2_CC20IC CC2_CC21IC CC2_CC22IC CC2_CC23IC CC2_CC24IC CC2_CC25IC CC2_CC26IC CC2_CC27IC CC2_CC28IC CC2_CC29IC CC2_CC30IC CC2_CC31IC CC2_T7IC CC2_T8IC GPT12E_T2IC GPT12E_T3IC GPT12E_T4IC GPT12E_T5IC GPT12E_T6IC
21
Source of Interrupt or PEC Service Request EX0IN EX1IN EX2IN EX3IN EX4IN EX5IN CAPCOM Register 16 CAPCOM Register 17 CAPCOM Register 18 CAPCOM Register 19 CAPCOM Register 20 CAPCOM Register 21 CAPCOM Register 22 CAPCOM Register 23 CAPCOM Register 24 CAPCOM Register 25 CAPCOM Register 26 CAPCOM Register 27 CAPCOM Register 28 CAPCOM Register 29 CAPCOM Register 30 CAPCOM Register 31 CAPCOM Timer 7 CAPCOM Timer 8 GPT1 Timer 2 GPT1 Timer 3 GPT1 Timer 4 GPT2 Timer 5 GPT2 Timer 6
Data Sheet
Vector Location1) xx'0060H xx'0064H xx'0068H xx'006CH xx'0070H xx'0074H xx'00C0H xx'00C4H xx'00C8H xx'00CCH xx'00D0H xx'00D4H xx'00D8H xx'00DCH xx'00E0H xx'00E4H xx'00E8H xx'00ECH xx'00F0H xx'0110H xx'0114H xx'0118H xx'00F4H xx'00F8H xx'0088H xx'008CH xx'0090H xx'0094H xx'0098H
Trap Number 18H / 24D 19H / 25D 1AH / 26D 1BH / 27D 1CH / 28D 1DH / 29D 30H / 48D 31H / 49D 32H / 50D 33H / 51D 34H / 52D 35H / 53D 36H / 54D 37H / 55D 38H / 56D 39H / 57D 3AH / 58D 3BH / 59D 3CH / 60D 44H / 68D 45H / 69D 46H / 70D 3DH / 61D 3EH / 62D 22H / 34D 23H / 35D 24H / 36D 25H / 37D 26H / 38D
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XC164KM Derivatives
Functional Description Table 4 XC164KM Interrupt Nodes (cont'd) Control Register GPT12E_CRIC ASC0_TIC ASC0_TBIC ASC0_RIC ASC0_EIC ASC0_ABIC SSC0_TIC SSC0_RIC SSC0_EIC PLLIC ASC1_TIC ASC1_TBIC ASC1_RIC ASC1_EIC ASC1_ABIC EOPIC SSC1_TIC SSC1_RIC SSC1_EIC CAN_0IC CAN_1IC CAN_2IC CAN_3IC CAN_4IC CAN_5IC CAN_6IC CAN_7IC RTC_IC - -
22
Source of Interrupt or PEC Service Request GPT2 CAPREL Register ASC0 Transmit ASC0 Transmit Buffer ASC0 Receive ASC0 Error ASC0 Autobaud SSC0 Transmit SSC0 Receive SSC0 Error PLL/OWD ASC1 Transmit ASC1 Transmit Buffer ASC1 Receive ASC1 Error ASC1 Autobaud End of PEC Subchannel SSC1 Transmit SSC1 Receive SSC1 Error CAN0 CAN1 CAN2 CAN3 CAN4 CAN5 CAN6 CAN7 RTC Unassigned node Unassigned node
Data Sheet
Vector Location1) xx'009CH xx'00A8H xx'011CH xx'00ACH xx'00B0H xx'017CH xx'00B4H xx'00B8H xx'00BCH xx'010CH xx'0120H xx'0178H xx'0124H xx'0128H xx'0108H xx'0130H xx'0144H xx'0148H xx'014CH xx'0150H xx'0154H xx'0158H xx'015CH xx'0164H xx'0168H xx'016CH xx'0170H xx'0174H xx'0040H xx'0044H
Trap Number 27H / 39D 2AH / 42D 47H / 71D 2BH / 43D 2CH / 44D 5FH / 95D 2DH / 45D 2EH / 46D 2FH / 47D 43H / 67D 48H / 72D 5EH / 94D 49H / 73D 4AH / 74D 42H / 66D 4CH / 76D 51H / 81D 52H / 82D 53H / 83D 54H / 84D 55H / 85D 56H / 86D 57H / 87D 59H / 89D 5AH / 90D 5BH / 91D 5CH / 92D 5DH / 93D 10H / 16D 11H / 17D
V1.2, 2007-03
XC164KM Derivatives
Functional Description Table 4 XC164KM Interrupt Nodes (cont'd) Control Register - - - - - - - - - - - - - - - - - - - - - Vector Location1) xx'0048H xx'004CH xx'0050H xx'0054H xx'0058H xx'005CH xx'0078H xx'007CH xx'0080H xx'0084H xx'00A0H xx'00A4H xx'00FCH xx'0100H xx'0104H xx'012CH xx'0134H xx'0138H xx'013CH xx'0140H xx'0160H Trap Number 12H / 18D 13H / 19D 14H / 20D 15H / 21D 16H / 22D 17H / 23D 1EH / 30D 1FH / 31D 20H / 32D 21H / 33D 28H / 40D 29H / 41D 3FH / 63D 40H / 64D 41H / 65D 4BH / 75D 4DH / 77D 4EH / 78D 4FH / 79D 50H / 80D 58H / 88D
Source of Interrupt or PEC Service Request Unassigned node Unassigned node Unassigned node Unassigned node Unassigned node Unassigned node Unassigned node Unassigned node Unassigned node Unassigned node Unassigned node Unassigned node Unassigned node Unassigned node Unassigned node Unassigned node Unassigned node Unassigned node Unassigned node Unassigned node Unassigned node
1) Register VECSEG defines the segment where the vector table is located to. Bitfield VECSC in register CPUCON1 defines the distance between two adjacent vectors. This table represents the default setting, with a distance of 4 (two words) between two vectors.
Data Sheet
23
V1.2, 2007-03
XC164KM Derivatives
Functional Description The XC164KM also provides an excellent mechanism to identify and to process exceptions or error conditions that arise during run-time, so-called `Hardware Traps'. Hardware traps cause immediate non-maskable system reaction which is similar to a standard interrupt service (branching to a dedicated vector table location). The occurrence of a hardware trap is additionally signified by an individual bit in the trap flag register (TFR). Except when another higher prioritized trap service is in progress, a hardware trap will interrupt any actual program execution. In turn, hardware trap services can normally not be interrupted by standard or PEC interrupts. Table 5 shows all of the possible exceptions or error conditions that can arise during runtime: Table 5 Hardware Trap Summary Trap Flag - RESET RESET RESET NMI STKOF STKUF SOFTBRK UNDOPC PACER PRTFLT ILLOPA - - NMITRAP STOTRAP STUTRAP SBRKTRAP BTRAP BTRAP BTRAP BTRAP - - xx'0000H xx'0000H xx'0000H xx'0008H xx'0010H xx'0018H xx'0020H xx'0028H xx'0028H xx'0028H xx'0028H 00H 00H 00H 02H 04H 06H 08H 0AH 0AH 0AH 0AH III III III II II II II I I I I - Current CPU Priority Trap Vector Vector Trap Trap 1) Location Number Priority
Exception Condition Reset Functions: * Hardware Reset * Software Reset * W-dog Timer Overflow Class A Hardware Traps: * Non-Maskable Interrupt * Stack Overflow * Stack Underflow * Software Break Class B Hardware Traps: * Undefined Opcode * PMI Access Error * Protected Instruction Fault * Illegal Word Operand Access Reserved Software Traps * TRAP Instruction
[2CH - 3CH] [0BH 0FH] Any Any [xx'0000H - [00H xx'01FCH] 7FH] in steps of 4H
1) Register VECSEG defines the segment where the vector table is located to. Bitfield VECSC in register CPUCON1 defines the distance between two adjacent vectors. This table represents the default setting, with a distance of 4 (two words) between two vectors.
Data Sheet
24
V1.2, 2007-03
XC164KM Derivatives
Functional Description
3.4
On-Chip Debug Support (OCDS)
The On-Chip Debug Support system provides a broad range of debug and emulation features built into the XC164KM. The user software running on the XC164KM can thus be debugged within the target system environment. The OCDS is controlled by an external debugging device via the debug interface, consisting of the IEEE-1149-conforming JTAG port and a break interface. The debugger controls the OCDS via a set of dedicated registers accessible via the JTAG interface. Additionally, the OCDS system can be controlled by the CPU, e.g. by a monitor program. An injection interface allows the execution of OCDS-generated instructions by the CPU. Multiple breakpoints can be triggered by on-chip hardware, by software, or by an external trigger input. Single stepping is supported as well as the injection of arbitrary instructions and read/write access to the complete internal address space. A breakpoint trigger can be answered with a CPU-halt, a monitor call, a data transfer, or/and the activation of an external signal. Tracing data can be obtained via the JTAG interface. The debug interface uses a set of 6 interface signals (4 JTAG lines, 2 break lines) to communicate with external circuitry. These interface signals are realized as alternate functions on Port 3 pins.
Data Sheet
25
V1.2, 2007-03
XC164KM Derivatives
Functional Description
3.5
Capture/Compare Unit (CAPCOM2)
The CAPCOM unit supports generation and control of timing sequences on up to 16 channels with a maximum resolution of 1 system clock cycle (8 cycles in staggered mode). The CAPCOM unit is typically used to handle high speed I/O tasks such as pulse and waveform generation, pulse width modulation (PWM), Digital to Analog (D/A) conversion, software timing, or time recording relative to external events. Two 16-bit timers (T7/T8) with reload registers provide two independent time bases for the capture/compare register array. The input clock for the timers is programmable to several prescaled values of the internal system clock, or may be derived from an overflow/underflow of timer T6 in module GPT2. This provides a wide range of variation for the timer period and resolution and allows precise adjustments to the application specific requirements. In addition, an external count input for CAPCOM timer T7 allows event scheduling for the capture/compare registers relative to external events. The capture/compare register array contains 16 dual purpose capture/compare registers, each of which may be individually allocated to either CAPCOM timer (T7 or T8, respectively), and programmed for capture or compare function. 10 registers of the CAPCOM2 module have each one port pin associated with it which serves as an input pin for triggering the capture function, or as an output pin to indicate the occurrence of a compare event. Table 6 Mode 0 Mode 1 Mode 2 Mode 3 Double Register Mode Single Event Mode Compare Modes (CAPCOM2) Function Interrupt-only compare mode; Several compare interrupts per timer period are possible Pin toggles on each compare match; Several compare events per timer period are possible Interrupt-only compare mode; Only one compare interrupt per timer period is generated Pin set `1' on match; pin reset `0' on compare timer overflow; Only one compare event per timer period is generated Two registers operate on one pin; Pin toggles on each compare match; Several compare events per timer period are possible Generates single edges or pulses; Can be used with any compare mode
Compare Modes
When a capture/compare register has been selected for capture mode, the current contents of the allocated timer will be latched (`captured') into the capture/compare
Data Sheet 26 V1.2, 2007-03
XC164KM Derivatives
Functional Description register in response to an external event at the port pin which is associated with this register. In addition, a specific interrupt request for this capture/compare register is generated. Either a positive, a negative, or both a positive and a negative external signal transition at the pin can be selected as the triggering event. The contents of all registers which have been selected for one of the five compare modes are continuously compared with the contents of the allocated timers. When a match occurs between the timer value and the value in a capture/compare register, specific actions will be taken based on the selected compare mode.
Data Sheet
27
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XC164KM Derivatives
Functional Description
Reload Reg. T7REL
fC C T7IN T6OUF CCxIO CCxIO
T7 Input Control
Timer T7
T7IRQ
CCxIRQ CCxIRQ Mode Control (Capture or Compare) Sixteen 16-bit Capture/ Compare Registers CCxIRQ T8 Input Control
CCxIO fC C T6OUF
Timer T8
T8IRQ
Reload Reg. T8REL CAPCOM2 provides channels x = 16 ... 31. (see signals CCxIO and CCxIRQ)
MCB05569_2
Figure 5
CAPCOM2 Unit Block Diagram
Data Sheet
28
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XC164KM Derivatives
Functional Description
3.6
General Purpose Timer (GPT12E) Unit
The GPT12E unit represents a very flexible multifunctional timer/counter structure which may be used for many different time related tasks such as event timing and counting, pulse width and duty cycle measurements, pulse generation, or pulse multiplication. The GPT12E unit incorporates five 16-bit timers which are organized in two separate modules, GPT1 and GPT2. Each timer in each module may operate independently in a number of different modes, or may be concatenated with another timer of the same module. Each of the three timers T2, T3, T4 of module GPT1 can be configured individually for one of four basic modes of operation, which are Timer, Gated Timer, Counter, and Incremental Interface Mode. In Timer Mode, the input clock for a timer is derived from the system clock, divided by a programmable prescaler, while Counter Mode allows a timer to be clocked in reference to external events. Pulse width or duty cycle measurement is supported in Gated Timer Mode, where the operation of a timer is controlled by the `gate' level on an external input pin. For these purposes, each timer has one associated port pin (TxIN) which serves as gate or clock input. The maximum resolution of the timers in module GPT1 is 4 system clock cycles. The count direction (up/down) for each timer is programmable by software or may additionally be altered dynamically by an external signal on a port pin (TxEUD) to facilitate e.g. position tracking. In Incremental Interface Mode the GPT1 timers (T2, T3, T4) can be directly connected to the incremental position sensor signals A and B via their respective inputs TxIN and TxEUD. Direction and count signals are internally derived from these two input signals, so the contents of the respective timer Tx corresponds to the sensor position. The third position sensor signal TOP0 can be connected to an interrupt input. Timer T3 has an output toggle latch (T3OTL) which changes its state on each timer overflow/underflow. The state of this latch may be output on pin T3OUT e.g. for time out monitoring of external hardware components. It may also be used internally to clock timers T2 and T4 for measuring long time periods with high resolution. In addition to their basic operating modes, timers T2 and T4 may be configured as reload or capture registers for timer T3. When used as capture or reload registers, timers T2 and T4 are stopped. The contents of timer T3 is captured into T2 or T4 in response to a signal at their associated input pins (TxIN). Timer T3 is reloaded with the contents of T2 or T4 triggered either by an external signal or by a selectable state transition of its toggle latch T3OTL. When both T2 and T4 are configured to alternately reload T3 on opposite state transitions of T3OTL with the low and high times of a PWM signal, this signal can be constantly generated without software intervention.
Data Sheet
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XC164KM Derivatives
Functional Description
T3CON.BPS1
f GPT
2n:1
Basic Clock Aux. Timer T2 Interrupt Request (T2IRQ)
T2IN T2EUD
T2 Mode Control
U/D Reload Capture
Interrupt Request (T3IRQ) T3 Mode Control
T3IN T3EUD
Core Timer T3 U/D
T3OTL Toggle Latch
T3OUT
Capture T4IN T4EUD T4 Mode Control Reload Aux. Timer T4 U/D Interrupt Request (T4IRQ)
MCA05563
Figure 6
Block Diagram of GPT1
With its maximum resolution of 2 system clock cycles, the GPT2 module provides precise event control and time measurement. It includes two timers (T5, T6) and a capture/reload register (CAPREL). Both timers can be clocked with an input clock which is derived from the CPU clock via a programmable prescaler or with external signals. The
Data Sheet
30
V1.2, 2007-03
XC164KM Derivatives
Functional Description count direction (up/down) for each timer is programmable by software or may additionally be altered dynamically by an external signal on a port pin (TxEUD). Concatenation of the timers is supported via the output toggle latch (T6OTL) of timer T6, which changes its state on each timer overflow/underflow. The state of this latch may be used to clock timer T5, and/or it may be output on pin T6OUT. The overflows/underflows of timer T6 can additionally be used to clock the CAPCOM2 timers, and to cause a reload from the CAPREL register. The CAPREL register may capture the contents of timer T5 based on an external signal transition on the corresponding port pin (CAPIN), and timer T5 may optionally be cleared after the capture procedure. This allows the XC164KM to measure absolute time differences or to perform pulse multiplication without software overhead. The capture trigger (timer T5 to CAPREL) may also be generated upon transitions of GPT1 timer T3's inputs T3IN and/or T3EUD. This is especially advantageous when T3 operates in Incremental Interface Mode.
Data Sheet
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XC164KM Derivatives
Functional Description
T6CON.BPS2
fGPT
2n:1
Basic Clock GPT2 Timer T5 T5 Mode Control Interrupt Request (T5IRQ)
T5IN
U/D Clear
Capture
CAPIN T3IN/ T3EUD
CAPREL Mode Control
GPT2 CAPREL Reload Clear
Interrupt Request (CRIRQ) Interrupt Request (T6IRQ) Toggle FF
T6IN
T6 Mode Control
GPT2 Timer T6 U/D
T6OTL
T6OUT T6OUF
MCA05564
Figure 7
Block Diagram of GPT2
Data Sheet
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XC164KM Derivatives
Functional Description
3.7
Real Time Clock
The Real Time Clock (RTC) module of the XC164KM is directly clocked via a separate clock driver with the prescaled on-chip main oscillator frequency (fRTC = fOSCm/32). It is therefore independent from the selected clock generation mode of the XC164KM. The RTC basically consists of a chain of divider blocks: * * * A selectable 8:1 divider (on - off) The reloadable 16-bit timer T14 The 32-bit RTC timer block (accessible via registers RTCH and RTCL), made of: - a reloadable 10-bit timer - a reloadable 6-bit timer - a reloadable 6-bit timer - a reloadable 10-bit timer
All timers count up. Each timer can generate an interrupt request. All requests are combined to a common node request.
fRTC
:8 RUN
MUX
Interrupt Sub Node CNT INT0 CNT INT1 CNT INT2
RTCINT CNT INT3
PRE
REL-Register T14REL 10 Bits 6 Bits 6 Bits 10 Bits
fCNT
T14 T14-Register
10 Bits
6 Bits
6 Bits
10 Bits
CNT-Register
MCB05568
Figure 8
RTC Block Diagram
Note: The registers associated with the RTC are not affected by a reset in order to maintain the correct system time even when intermediate resets are executed.
Data Sheet
33
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XC164KM Derivatives
Functional Description The RTC module can be used for different purposes: * * * * System clock to determine the current time and date, optionally during idle mode, sleep mode, and power down mode Cyclic time based interrupt, to provide a system time tick independent of CPU frequency and other resources, e.g. to wake up regularly from idle mode 48-bit timer for long term measurements (maximum timespan is > 100 years) Alarm interrupt for wake-up on a defined time
3.8
Asynchronous/Synchronous Serial Interfaces (ASC0/ASC1)
The Asynchronous/Synchronous Serial Interfaces ASC0/ASC1 (USARTs) provide serial communication with other microcontrollers, processors, terminals or external peripheral components. They are upward compatible with the serial ports of the Infineon 8-bit microcontroller families and support full-duplex asynchronous communication and halfduplex synchronous communication. A dedicated baudrate generator with a fractional divider precisely generates all standard baud rates without oscillator tuning. For transmission, reception, error handling, and baud rate detection 5 separate interrupt vectors are provided. In asynchronous mode, 8- or 9-bit data frames (with optional parity bit) are transmitted or received, preceded by a start bit and terminated by one or two stop bits. For multiprocessor communication, a mechanism to distinguish address from data bytes has been included (8-bit data plus wake-up bit mode). IrDA data transmissions up to 115.2 kbit/s with fixed or programmable IrDA pulse width are supported. In synchronous mode, bytes (8 bits) are transmitted or received synchronously to a shift clock which is generated by the ASC0/1. The LSB is always shifted first. In both modes, transmission and reception of data is FIFO-buffered. An autobaud detection unit allows to detect asynchronous data frames with its baudrate and mode with automatic initialization of the baudrate generator and the mode control bits. A number of optional hardware error detection capabilities has been included to increase the reliability of data transfers. A parity bit can automatically be generated on transmission or be checked on reception. Framing error detection allows to recognize data frames with missing stop bits. An overrun error will be generated, if the last character received has not been read out of the receive buffer register at the time the reception of a new character is complete. Summary of Features * Full-duplex asynchronous operating modes - 8- or 9-bit data frames, LSB first, one or two stop bits, parity generation/checking - Baudrate from 2.5 Mbit/s to 0.6 bit/s (@ 40 MHz) - Multiprocessor mode for automatic address/data byte detection - Support for IrDA data transmission/reception up to max. 115.2 kbit/s (@ 40 MHz)
34 V1.2, 2007-03
Data Sheet
XC164KM Derivatives
Functional Description * * * * - Auto baudrate detection Half-duplex 8-bit synchronous operating mode at 5 Mbit/s to 406.9 bit/s (@ 40 MHz) Buffered transmitter/receiver with FIFO support (8 entries per direction) Loop-back option available for testing purposes Interrupt generation on transmitter buffer empty condition, last bit transmitted condition, receive buffer full condition, error condition (frame, parity, overrun error), start and end of an autobaud detection
3.9
High Speed Synchronous Serial Channels (SSC0/SSC1)
The High Speed Synchronous Serial Channels SSC0/SSC1 support full-duplex and halfduplex synchronous communication. It may be configured so it interfaces with serially linked peripheral components, full SPI functionality is supported. A dedicated baud rate generator allows to set up all standard baud rates without oscillator tuning. For transmission, reception and error handling three separate interrupt vectors are provided. The SSC transmits or receives characters of 2 ... 16 bits length synchronously to a shift clock which can be generated by the SSC (master mode) or by an external master (slave mode). The SSC can start shifting with the LSB or with the MSB and allows the selection of shifting and latching clock edges as well as the clock polarity. A number of optional hardware error detection capabilities has been included to increase the reliability of data transfers. Transmit error and receive error supervise the correct handling of the data buffer. Phase error and baudrate error detect incorrect serial data. Summary of Features * * * * Master or Slave mode operation Full-duplex or Half-duplex transfers Baudrate generation from 20 Mbit/s to 305.18 bit/s (@ 40 MHz) Flexible data format - Programmable number of data bits: 2 to 16 bits - Programmable shift direction: LSB-first or MSB-first - Programmable clock polarity: idle low or idle high - Programmable clock/data phase: data shift with leading or trailing clock edge Loop back option available for testing purposes Interrupt generation on transmitter buffer empty condition, receive buffer full condition, error condition (receive, phase, baudrate, transmit error) Three pin interface with flexible SSC pin configuration
* * *
Data Sheet
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XC164KM Derivatives
Functional Description
3.10
TwinCAN Module
The integrated TwinCAN module handles the completely autonomous transmission and reception of CAN frames in accordance with the CAN specification V2.0 part B (active), i.e. the on-chip TwinCAN module can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. Two Full-CAN nodes share the TwinCAN module's resources to optimize the CAN bus traffic handling and to minimize the CPU load. The module provides up to 32 message objects, which can be assigned to one of the CAN nodes and can be combined to FIFOstructures. Each object provides separate masks for acceptance filtering. The flexible combination of Full-CAN functionality and FIFO architecture reduces the efforts to fulfill the real-time requirements of complex embedded control applications. Improved CAN bus monitoring functionality as well as the number of message objects permit precise and comfortable CAN bus traffic handling. Gateway functionality allows automatic data exchange between two separate CAN bus systems, which reduces CPU load and improves the real time behavior of the entire system. The bit timing for both CAN nodes is derived from the master clock and is programmable up to a data rate of 1 Mbit/s. Each CAN node uses two pins of Port 9 to interface to an external bus transceiver. The interface pins are assigned via software.
TwinCAN Module Kernel Clock Control
fCAN
CAN Node A
CAN Node B
TxDCA RxDCA Port Control TxDCB RxDCB
Address Decoder
Message Object Buffer
Interrupt Control
TwinCAN Control
MCB05567
Figure 9
TwinCAN Module Block Diagram
Data Sheet
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Functional Description Summary of Features * * * * * CAN functionality according to CAN specification V2.0 B active Data transfer rate up to 1 Mbit/s Flexible and powerful message transfer control and error handling capabilities Full-CAN functionality and Basic CAN functionality for each message object 32 flexible message objects - Assignment to one of the two CAN nodes - Configuration as transmit object or receive object - Concatenation to a 2-, 4-, 8-, 16-, or 32-message buffer with FIFO algorithm - Handling of frames with 11-bit or 29-bit identifiers - Individual programmable acceptance mask register for filtering for each object - Monitoring via a frame counter - Configuration for Remote Monitoring Mode Up to eight individually programmable interrupt nodes can be used CAN Analyzer Mode for bus monitoring is implemented
* *
3.11
LXBus Controller (EBC)
The EBC only controls accesses to resources connected to the on-chip LXBus. The LXBus is an internal representation of the external bus and allows accessing integrated peripherals and modules in the same way as external components. The TwinCAN module is connected and accessed via the LXBus.
Data Sheet
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Functional Description
3.12
Watchdog Timer
The Watchdog Timer represents one of the fail-safe mechanisms which have been implemented to prevent the controller from malfunctioning for longer periods of time. The Watchdog Timer is always enabled after a reset of the chip, and can be disabled until the EINIT instruction has been executed (compatible mode), or it can be disabled and enabled at any time by executing instructions DISWDT and ENWDT (enhanced mode). Thus, the chip's start-up procedure is always monitored. The software has to be designed to restart the Watchdog Timer before it overflows. If, due to hardware or software related failures, the software fails to do so, the Watchdog Timer overflows and generates an internal hardware reset. The Watchdog Timer is a 16-bit timer, clocked with the system clock divided by 2/4/128/256. The high byte of the Watchdog Timer register can be set to a prespecified reload value (stored in WDTREL) in order to allow further variation of the monitored time interval. Each time it is serviced by the application software, the high byte of the Watchdog Timer is reloaded and the low byte is cleared. Thus, time intervals between 13 s and 419 ms can be monitored (@ 40 MHz). The default Watchdog Timer interval after reset is 3.28 ms (@ 40 MHz).
Data Sheet
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XC164KM Derivatives
Functional Description
3.13
Clock Generation
The Clock Generation Unit uses a programmable on-chip PLL with multiple prescalers to generate the clock signals for the XC164KM with high flexibility. The master clock fMC is the reference clock signal, and is used for TwinCAN and is output to the external system. The CPU clock fCPU and the system clock fSYS are derived from the master clock either directly (1:1) or via a 2:1 prescaler (fSYS = fCPU = fMC / 2). See also Section 4.3.1. The on-chip oscillator can drive an external crystal or accepts an external clock signal. The oscillator clock frequency can be multiplied by the on-chip PLL (by a programmable factor) or can be divided by a programmable prescaler factor. If the bypass mode is used (direct drive or prescaler) the PLL can deliver an independent clock to monitor the clock signal generated by the on-chip oscillator. This PLL clock is independent from the XTAL1 clock. When the expected oscillator clock transitions are missing the Oscillator Watchdog (OWD) activates the PLL Unlock/OWD interrupt node and supplies the CPU with an emergency clock, the PLL clock signal. Under these circumstances the PLL will oscillate with its basic frequency. The oscillator watchdog can be disabled by switching the PLL off. This reduces power consumption, but also no interrupt request will be generated in case of a missing oscillator clock.
Data Sheet
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Functional Description
3.14
Parallel Ports
The XC164KM provides up to 47 I/O lines which are organized into three input/output ports and one input port. All port lines are bit-addressable, and all input/output lines are individually (bit-wise) programmable as inputs or outputs via direction registers. The I/O ports are true bidirectional ports which are switched to high impedance state when configured as inputs. The output drivers of some I/O ports can be configured (pin by pin) for push/pull operation or open-drain operation via control registers. During the internal reset, all port pins are configured as inputs. The edge characteristics (shape) and driver characteristics (output current) of the port drivers can be selected via registers POCONx. The input threshold of some ports is selectable (TTL or CMOS like), where the special CMOS like input threshold reduces noise sensitivity due to the input hysteresis. The input threshold may be selected individually for each byte of the respective ports. All port lines have programmable alternate input or output functions associated with them. All port lines that are not used for these alternate functions may be used as general purpose IO lines. Table 7 Port PORT1 Port 3 Summary of the XC164KM's Parallel Ports Control Pad drivers Pad drivers, Open drain, Input threshold - Pad drivers, Open drain, Input threshold Alternate Functions Capture inputs or compare outputs, Serial interface lines Timer control signals, serial interface lines, System clock output CLKOUT (or FOUT) Timer control signals Capture inputs or compare outputs CAN interface lines1)
Port 5 Port 9
1) Can be assigned by software.
Data Sheet
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XC164KM Derivatives
Functional Description
3.15
Power Management
The XC164KM provides several means to control the power it consumes either at a given time or averaged over a certain timespan. Three mechanisms can be used (partly in parallel): * Power Saving Modes switch the XC164KM into a special operating mode (control via instructions). Idle Mode stops the CPU while the peripherals can continue to operate. Sleep Mode and Power Down Mode stop all clock signals and all operation (RTC may optionally continue running). Sleep Mode can be terminated by external interrupt signals. Clock Generation Management controls the distribution and the frequency of internal and external clock signals. While the clock signals for currently inactive parts of logic are disabled automatically, the user can reduce the XC164KM's CPU clock frequency which drastically reduces the consumed power. External circuitry can be controlled via the programmable frequency output FOUT. Peripheral Management permits temporary disabling of peripheral modules (control via register SYSCON3). Each peripheral can separately be disabled/enabled.
*
*
The on-chip RTC supports intermittent operation of the XC164KM by generating cyclic wake-up signals. This offers full performance to quickly react on action requests while the intermittent sleep phases greatly reduce the average power consumption of the system.
Data Sheet
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Functional Description
3.16
Instruction Set Summary
Table 8 lists the instructions of the XC164KM in a condensed way. The various addressing modes that can be used with a specific instruction, the operation of the instructions, parameters for conditional execution of instructions, and the opcodes for each instruction can be found in the "Instruction Set Manual". This document also provides a detailed description of each instruction. Table 8 Mnemonic ADD(B) ADDC(B) SUB(B) SUBC(B) MUL(U) DIV(U) DIVL(U) CPL(B) NEG(B) AND(B) OR(B) XOR(B) BCLR/BSET BMOV(N) BCMP BFLDH/BFLDL CMP(B) CMPD1/2 CMPI1/2 PRIOR SHL/SHR Instruction Set Summary Description Add word (byte) operands Add word (byte) operands with Carry Subtract word (byte) operands Subtract word (byte) operands with Carry (Un)Signed multiply direct GPR by direct GPR (16- x 16-bit) Bytes 2/4 2/4 2/4 2/4 2
(Un)Signed divide register MDL by direct GPR (16-/16-bit) 2 (Un)Signed long divide reg. MD by direct GPR (32-/16-bit) 2 Complement direct word (byte) GPR Negate direct word (byte) GPR Bitwise AND, (word/byte operands) Bitwise OR, (word/byte operands) Bitwise exclusive OR, (word/byte operands) Clear/Set direct bit Move (negated) direct bit to direct bit Compare direct bit to direct bit Bitwise modify masked high/low byte of bit-addressable direct word memory with immediate data Compare word (byte) operands Compare word data to GPR and decrement GPR by 1/2 Compare word data to GPR and increment GPR by 1/2 Determine number of shift cycles to normalize direct word GPR and store result in direct word GPR Shift left/right direct word GPR 2 2 2/4 2/4 2/4 2 4 4 4 4 2/4 2/4 2/4 2 2
BAND/BOR/BXOR AND/OR/XOR direct bit with direct bit
Data Sheet
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Functional Description Table 8 Mnemonic ROL/ROR ASHR MOV(B) MOVBS/Z JMPA/I/R JMPS JB(C) JNB(S) CALLA/I/R CALLS PCALL TRAP PUSH/POP SCXT RET(P) RETS RETI SBRK SRST IDLE PWRDN SRVWDT DISWDT/ENWDT EINIT ATOMIC EXTR EXTP(R) EXTS(R)
Data Sheet
Instruction Set Summary (cont'd) Description Rotate left/right direct word GPR Arithmetic (sign bit) shift right direct word GPR Move word (byte) data Move byte operand to word op. with sign/zero extension Jump absolute/indirect/relative if condition is met Jump absolute to a code segment Jump relative if direct bit is set (and clear bit) Jump relative if direct bit is not set (and set bit) Call absolute subroutine in any code segment Push direct word register onto system stack and call absolute subroutine Call interrupt service routine via immediate trap number Push/pop direct word register onto/from system stack Push direct word register onto system stack and update register with word operand Return from intra-segment subroutine (and pop direct word register from system stack) Return from inter-segment subroutine Return from interrupt service subroutine Software Break Software Reset Enter Idle Mode Enter Power Down Mode (supposes NMI-pin being low) Service Watchdog Timer Disable/Enable Watchdog Timer End-of-Initialization Register Lock Begin ATOMIC sequence Begin EXTended Register sequence Begin EXTended Page (and Register) sequence Begin EXTended Segment (and Register) sequence
43
Bytes 2 2 2/4 2/4 4 4 4 4 4 4 2 2 4 2 2 2 2 4 4 4 4 4 4 2 2 2/4 2/4
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XC164KM Derivatives
Functional Description Table 8 Mnemonic NOP CoMUL/CoMAC CoADD/CoSUB Co(A)SHR CoSHL CoLOAD/STORE CoCMP CoMAX/MIN CoABS/CoRND CoMOV CoNEG/NOP Instruction Set Summary (cont'd) Description Null operation Multiply (and accumulate) Add/Subtract (Arithmetic) Shift right Shift left Load accumulator/Store MAC register Compare Maximum/Minimum Absolute value/Round accumulator Data move Negate accumulator/Null operation Bytes 2 4 4 4 4 4 4 4 4 4 4
Data Sheet
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Electrical Parameters
4
Electrical Parameters
The operating range for the XC164KM is defined by its electrical parameters. For proper operation the indicated limitations must be respected when designing a system.
4.1
General Parameters
These parameters are valid for all subsequent descriptions, unless otherwise noted. Table 9 Parameter Storage temperature Junction temperature Voltage on VDDI pins with respect to ground (VSS) Voltage on VDDP pins with respect to ground (VSS) Voltage on any pin with respect to ground (VSS) Input current on any pin during overload condition Absolute sum of all input currents during overload condition Absolute Maximum Ratings Symbol Limit Values Min. Max. 150 150 3.25 6.2 C C V V V mA mA
1)
Unit
Notes
TST TJ VDDI VDDP VIN
- -
-65 -40 -0.5 -0.5 -0.5 -10 -
Under bias - -
2)
VDDP +
0.5 10 |100|
- -
1) Moisture Sensitivity Level (MSL) 3, conforming to Jedec J-STD-020C for 260 C. 2) Input pin XTAL1 belongs to the core voltage domain. Therefore, input voltages must be within the range defined for VDDI.
Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. During absolute maximum rating overload conditions (VIN > VDDP or VIN < VSS) the voltage on VDDP pins with respect to ground (VSS) must not exceed the values defined by the absolute maximum ratings.
Data Sheet
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Electrical Parameters Operating Conditions The following operating conditions must not be exceeded to ensure correct operation of the XC164KM. All parameters specified in the following sections refer to these operating conditions, unless otherwise noticed. Table 10 Parameter Digital supply voltage for the core Digital supply voltage for IO pads Digital ground voltage Operating Condition Parameters Symbol Limit Values Min. Max. 2.7 5.5 - 5 V V V V mA 5.0 x 10-3 - 1.0 x 10-2 - 50 50 70 85 125 mA pF C C C Active mode, fCPU = fCPUmax1) Active mode2)3) 2.35 4.4 -0.5 0 -5 - - |IOV| - - 0 -40 -40 Unit Notes
VDDI VDDP
Supply Voltage Difference VDD
VDDP - VDDI4)
Reference voltage Per IO pin5)6)
VSS Overload current IOV Overload current coupling KOVD
factor for digital I/O pins
7)
IOV > 0 IOV < 0
6)
Absolute sum of overload currents External Load Capacitance Ambient temperature
CL TA
Pin drivers in default mode8) SAB-XC164... SAF-XC164... SAK-XC164...
1) fCPUmax = 40 MHz for devices marked ... 40F, fCPUmax = 20 MHz for devices marked ... 20F. 2) External circuitry must guarantee low-level at the RSTIN pin at least until both power supply voltages have reached the operating range. 3) The specified voltage range is allowed for operation. The range limits may be reached under extreme operating conditions. However, specified parameters, such as leakage currents, refer to the standard operating voltage range of VDDP = 4.75 V to 5.25 V. 4) This limitation must be fulfilled under all operating conditions including power-ramp-up, power-ramp-down, and power-save modes. 5) Overload conditions occur if the standard operating conditions are exceeded, i.e. the voltage on any pin exceeds the specified range: VOV > VDDP + 0.5 V (IOV > 0) or VOV < VSS - 0.5 V (IOV < 0). The absolute sum of input overload currents on all pins may not exceed 50 mA. The supply voltages must remain within the specified limits. Proper operation is not guaranteed if overload conditions occur on functional pins such as XTAL1. 6) Not subject to production test - verified by design/characterization.
Data Sheet
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XC164KM Derivatives
Electrical Parameters
7) An overload current (IOV) through a pin injects a certain error current (IINJ) into the adjacent pins. This error current adds to the respective pin's leakage current (IOZ). The amount of error current depends on the overload current and is defined by the overload coupling factor KOV. The polarity of the injected error current is inverse compared to the polarity of the overload current that produces it. The total current through a pin is |ITOT| = |IOZ| + (|IOV| x KOV). The additional error current may distort the input voltage on analog inputs. 8) The timing is valid for pin drivers operating in default current mode (selected after reset). Reducing the output current may lead to increased delays or reduced driving capability (CL).
Parameter Interpretation The parameters listed in the following partly represent the characteristics of the XC164KM and partly its demands on the system. To aid in interpreting the parameters right, when evaluating them for a design, they are marked in column "Symbol": CC (Controller Characteristics): The logic of the XC164KM will provide signals with the respective characteristics. SR (System Requirement): The external system must provide signals with the respective characteristics to the XC164KM.
Data Sheet
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Electrical Parameters
4.2
DC Parameters
These parameters are static or average values, which may be exceeded during switching transitions (e.g. output current). Table 11 Parameter Input low voltage TTL (all except XTAL1) Input low voltage XTAL12) Input low voltage (Special Threshold) DC Characteristics (Operating Conditions apply)1) Symbol Min. Limit Values Max. 0.2 x VDDP V - 0.1 0.3 x VDDI 0.45 x V V - -
3)
Unit Test Condition
VIL VILC VILS
SR SR SR SR SR SR
-0.5 -0.5 -0.5 0.2 x VDDP + 0.9 0.7 x VDDI
Input high voltage TTL VIH (all except XTAL1) Input high voltage XTAL12) Input high voltage (Special Threshold) Input Hysteresis (Special Threshold) Output low voltage Output high voltage6)
VDDP VDDP + 0.5 V VDDI + 0.5 V
- -
3)
VIHC VIHS
HYS
0.8 x VDDP VDDP + 0.5 V - 0.2 0.04 x - V
VDDP VOL VOH
CC - - 1.0 0.45 - 300 200 V V V V nA nA nA A A
Series resistance = 0 3)
VDDP in [V],
CC VDDP - 1.0 -
VDDP 0.45 Input leakage current (Port 5)7)
IOL IOLmax4) IOL IOLnom4)5) IOH IOHmax4) IOH IOHnom4)5)
0 V < VIN < VDDP, TA 125 C 0 V < VIN < VDDP, TA 85 C12)
IOZ1
CC -
Input leakage current (all other8))7) Configuration pull-up current9)
IOZ2 ICPUH ICPUL11)
10)
CC - - -100
500 -10 -
VDDP VIN = VIHmin VIN = VILmax
0.45 V < VIN <
Data Sheet
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XC164KM Derivatives
Electrical Parameters Table 11 Parameter XTAL1 input current Pin capacitance12) (digital inputs/outputs) DC Characteristics (Operating Conditions apply)1) (cont'd) Symbol Min. Limit Values Max. 20 10 A pF 0 V < VIN < VDDI - CC - CC - Unit Test Condition
IIL CIO
1) Keeping signal levels within the limits specified in this table, ensures operation without overload conditions. For signal levels outside these specifications, also refer to the specification of the overload current IOV. 2) If XTAL1 is driven by a crystal, reaching an amplitude (peak to peak) of 0.4 x VDDI is sufficient. 3) This parameter is tested for P3, P9. 4) The maximum deliverable output current of a port driver depends on the selected output driver mode, see Table 12, Current Limits for Port Output Drivers. The limit for pin groups must be respected. 5) As a rule, with decreasing output current the output levels approach the respective supply level (VOL VSS, VOH VDDP). However, only the levels for nominal output currents are guaranteed. 6) This specification is not valid for outputs which are switched to open drain mode. In this case the respective output will float and the voltage results from the external circuitry. 7) An additional error current (IINJ) will flow if an overload current flows through an adjacent pin. Please refer to the definition of the overload coupling factor KOV. 8) The driver of P3.15 is designed for faster switching, because this pin can deliver the system clock (CLKOUT). The maximum leakage current for P3.15 is, therefore, increased to 1 A. 9) During a hardware reset this specification is valid for configuration on P1H.4, P1H.5, P9.4 and P9.5. After a hardware reset this specification is valid for NMI. 10) The maximum current may be drawn while the respective signal line remains inactive. 11) The minimum current must be drawn to drive the respective signal line active. 12) Not subject to production test - verified by design/characterization.
Table 12
Current Limits for Port Output Drivers Maximum Output Current (IOLmax, -IOHmax)1) 10 mA 4.0 mA 0.5 mA Nominal Output Current (IOLnom, -IOHnom) 2.5 mA 1.0 mA 0.1 mA
Port Output Driver Mode Strong driver Medium driver Weak driver
1) An output current above |IOXnom| may be drawn from up to three pins at the same time. For any group of 16 neighboring port output pins the total output current in each direction (IOL and -IOH) must remain below 50 mA.
Data Sheet
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Electrical Parameters Table 13 Parameter Power supply current (active) with all peripherals active Power Consumption XC164KM (Operating Conditions apply) SymLimit Values bol Min. Max. Unit Test Condition mA mA mA mA mA mA
IDDI
- -
15 + 2.6 x fCPU 10 + 2.6 x fCPU 5 15 + 1.2 x fCPU 10 + 1.2 x fCPU 84,000 x e-
-16F derivatives
fCPU in [MHz]1)2), fCPU in [MHz]1)2),
3)
-4F/8F derivatives
Pad supply current Idle mode supply current with all peripherals active
IDDP IIDX
- - -
fCPU in [MHz]2), fCPU in [MHz]2),
-16F derivatives -4F/8F derivatives
Sleep and Power down mode supply current caused by leakage4)
IPDL5) -
= 4380 / (273 + TJ) -16F derivatives mA = 4670 / (273 + TJ) -4F/8F derivatives
VDDI = VDDImax6) TJ in [C]
- Sleep and Power down mode IPDM7) - supply current caused by leakage and the RTC running, clocked by the main oscillator4)
128,000 x e-
0.6 + mA 0.02 x fOSC + IPDL
VDDI = VDDImax fOSC in [MHz]
1) During Flash programming or erase operations the supply current is increased by max. 5 mA. 2) The supply current is a function of the operating frequency. This dependency is illustrated in Figure 10. These parameters are tested at VDDImax and maximum CPU clock frequency with all outputs disconnected and all inputs at VIL or VIH. 3) The pad supply voltage pins (VDDP) mainly provides the current consumed by the pin output drivers. A small amount of current is consumed even though no outputs are driven, because the drivers' input stages are switched and also the Flash module draws some power from the VDDP supply. 4) The total supply current in Sleep and Power down mode is the sum of the temperature dependent leakage current and the frequency dependent current for RTC and main oscillator. 5) This parameter is determined mainly by the transistor leakage currents. This current heavily depends on the junction temperature (see Figure 12). The junction temperature TJ is the same as the ambient temperature TA if no current flows through the port output drivers. Otherwise, the resulting temperature difference must be taken into account. 6) All inputs (including pins configured as inputs) at 0 V to 0.1 V or at VDDP - 0.1 V to VDDP, all outputs (including pins configured as outputs) disconnected. This parameter is tested at 25 C and is valid for TJ 25 C. 7) This parameter is determined mainly by the current consumed by the oscillator switched to low gain mode (see Figure 11). This current, however, is influenced by the external oscillator circuitry (crystal, capacitors). The given values refer to a typical circuitry and may change in case of a not optimized external oscillator circuitry.
Data Sheet
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Electrical Parameters
I [mA]
-16F 140
IDDImax
-4F/8F
120
-16F
IDDItyp
-4F/8F
100
80
IIDXmax
-4F/8F 60 -16F
-16F
IIDXtyp
-4F/8F
40
20
10 Figure 10
20
30
40
fCPU [MHz]
Supply/Idle Current as a Function of Operating Frequency
Data Sheet
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Electrical Parameters
I [mA]
3.0
2.0
1.0
IPDMmax IPDMtyp
4 Figure 11
8
12
16
fOSC [MHz]
Sleep and Power Down Supply Current due to RTC and Oscillator Running, as a Function of Oscillator Frequency
IPDL
[mA] 1.5 -16F 1.0
0.5
-4F/8F
-50 Figure 12
0
50
100
150
TJ [C]
Sleep and Power Down Leakage Supply Current as a Function of Temperature
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Data Sheet
XC164KM Derivatives
Electrical Parameters
4.3
AC Parameters
These parameters describe the dynamic behavior of the XC164KM.
4.3.1
Definition of Internal Timing
The internal operation of the XC164KM is controlled by the internal master clock fMC. The master clock signal fMC can be generated from the oscillator clock signal fOSC via different mechanisms. The duration of master clock periods (TCMs) and their variation (and also the derived external timing) depend on the used mechanism to generate fMC. This influence must be regarded when calculating the timings for the XC164KM.
Phase Locked Loop Operation (1:N)
f OSC f MC
TCM Direct Clock Drive (1:1)
f OSC f MC
TCM Prescaler Operation (N:1)
f OSC f MC
TCM
MCT05555
Figure 13
Generation Mechanisms for the Master Clock
Note: The example for PLL operation shown in Figure 13 refers to a PLL factor of 1:4, the example for prescaler operation refers to a divider factor of 2:1.
Data Sheet
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Electrical Parameters The used mechanism to generate the master clock is selected by register PLLCON. CPU and EBC are clocked with the CPU clock signal fCPU. The CPU clock can have the same frequency as the master clock (fCPU = fMC) or can be the master clock divided by two: fCPU = fMC / 2. This factor is selected by bit CPSYS in register SYSCON1. The specification of the external timing (AC Characteristics) depends on the period of the CPU clock, called "TCP". The other peripherals are supplied with the system clock signal fSYS which has the same frequency as the CPU clock signal fCPU. Bypass Operation When bypass operation is configured (PLLCTRL = 0xB) the master clock is derived from the internal oscillator (input clock signal XTAL1) through the input- and outputprescalers:
fMC = fOSC / ((PLLIDIV + 1) x (PLLODIV + 1)).
If both divider factors are selected as `1' (PLLIDIV = PLLODIV = `0') the frequency of fMC directly follows the frequency of fOSC so the high and low time of fMC is defined by the duty cycle of the input clock fOSC. The lowest master clock frequency is achieved by selecting the maximum values for both divider factors:
fMC = fOSC / ((3 + 1) x (14 + 1)) = fOSC / 60.
Phase Locked Loop (PLL) When PLL operation is configured (PLLCTRL = 11B) the on-chip phase locked loop is enabled and provides the master clock. The PLL multiplies the input frequency by the factor F (fMC = fOSC x F) which results from the input divider, the multiplication factor, and the output divider (F = PLLMUL+1 / (PLLIDIV+1 x PLLODIV+1)). The PLL circuit synchronizes the master clock to the input clock. This synchronization is done smoothly, i.e. the master clock frequency does not change abruptly. Due to this adaptation to the input clock the frequency of fMC is constantly adjusted so it is locked to fOSC. The slight variation causes a jitter of fMC which also affects the duration of individual TCMs. The timing listed in the AC Characteristics refers to TCPs. Because fCPU is derived from fMC, the timing must be calculated using the minimum TCP possible under the respective circumstances. The actual minimum value for TCP depends on the jitter of the PLL. As the PLL is constantly adjusting its output frequency so it corresponds to the applied input frequency (crystal or oscillator) the relative deviation for periods of more than one TCP is lower than for one single TCP (see formula and Figure 14).
Data Sheet
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XC164KM Derivatives
Electrical Parameters This is especially important for bus cycles using waitstates and e.g. for the operation of timers, serial interfaces, etc. For all slower operations and longer periods (e.g. pulse train generation or measurement, lower baudrates, etc.) the deviation caused by the PLL jitter is negligible. The value of the accumulated PLL jitter depends on the number of consecutive VCO output cycles within the respective timeframe. The VCO output clock is divided by the output prescaler (K = PLLODIV+1) to generate the master clock signal fMC. Therefore, the number of VCO cycles can be represented as K x N, where N is the number of consecutive fMC cycles (TCM). For a period of N x TCM the accumulated PLL jitter is defined by the deviation DN: DN [ns] = (1.5 + 6.32 x N / fMC); fMC in [MHz], N = number of consecutive TCMs. So, for a period of 3 TCMs @ 20 MHz and K = 12: D3 = (1.5 + 6.32 x 3 / 20) = 2.448 ns. This formula is applicable for K x N < 95. For longer periods the K x N = 95 value can be used. This steady value can be approximated by: DNmax [ns] = (1.5 + 600 / (K x fMC)).
Acc. jitter DN ns 8 7 6 5 4 3 2 1 0 40 MHz
K = 12
K=8 K=6 K=5
K = 15 K = 10
10 MHz 20 MHz
01
5
10
15
20
25
N
MCD05566
Figure 14
Approximated Accumulated PLL Jitter
Note: The bold lines indicate the minimum accumulated jitter which can be achieved by selecting the maximum possible output prescaler factor K.
Data Sheet
55
V1.2, 2007-03
XC164KM Derivatives
Electrical Parameters Different frequency bands can be selected for the VCO, so the operation of the PLL can be adjusted to a wide range of input and output frequencies: Table 14 00 01 10 11 VCO Bands for PLL Operation1) VCO Frequency Range 100 ... 150 MHz 150 ... 200 MHz 200 ... 250 MHz Reserved Base Frequency Range 20 ... 80 MHz 40 ... 130 MHz 60 ... 180 MHz
PLLCON.PLLVB
1) Not subject to production test - verified by design/characterization.
Data Sheet
56
V1.2, 2007-03
XC164KM Derivatives
Electrical Parameters
4.3.2
On-chip Flash Operation
The XC164KM's Flash module delivers data within a fixed access time (see Table 15). Accesses to the Flash module are controlled by the PMI and take 1+WS clock cycles, where WS is the number of Flash access waitstates selected via bitfield WSFLASH in register IMBCTRL. The resulting duration of the access phase must cover the access time tACC of the Flash array. The required Flash waitstates depend on the actual system frequency. The Flash access waitstates only affect non-sequential accesses. Due to prefetching mechanisms, the performance for sequential accesses (depending on the software structure) is only partially influenced by waitstates. In typical applications, eliminating one waitstate increases the average performance by 5% ... 15%. Table 15 Parameter Flash module access time Flash Characteristics (Operating Conditions apply) Symbol Min. Limit Values Typ. - 22) 2002) Max. 501) 5 500 ns ms ms Unit
tACC CC - Programming time per 128-byte block tPR CC - tER CC - Erase time per sector
1) The actual access time is influenced by the system frequency, see Table 16. 2) Programming and erase time depends on the system frequency. Typical values are valid for 40 MHz.
Example: For an operating frequency of 40 MHz (clock cycle = 25 ns), the Flash accesses must be executed with 1 waitstate: ((1+1) x 25 ns) 50 ns. Table 16 indicates the interrelation of waitstates and system frequency. Table 16 Flash Access Waitstates Frequency Range
Required Waitstates 0 WS (WSFLASH = 00B) 1 WS (WSFLASH = 01B)
fCPU 20 MHz fCPU 40 MHz
Note: The maximum achievable system frequency is limited by the properties of the respective derivative, i.e. 40 MHz (or 20 MHz for XC164KM-xF20F devices).
Data Sheet
57
V1.2, 2007-03
XC164KM Derivatives
Electrical Parameters
4.3.3
External Clock Drive XTAL1
These parameters define the external clock supply for the XC164KM. Table 17 Parameter Oscillator period High time2) Low time
2) 2)
External Clock Drive Characteristics (Operating Conditions apply) Symbol Min. Limit Values Max. 2501) - - 8 8 ns ns ns ns ns SR SR SR SR SR 25 6 6 - - Unit
Rise time
Fall time2)
tOSC t1 t2 t3 t4
1) The maximum limit is only relevant for PLL operation to ensure the minimum input frequency for the PLL. 2) The clock input signal must reach the defined levels VILC and VIHC.
t1
0.5 V DDI
t3
t4 V IHC V ILC
t2 t OSC
MCT05572
Figure 15
External Clock Drive XTAL1
Note: If the on-chip oscillator is used together with a crystal or a ceramic resonator, the oscillator frequency is limited to a range of 4 MHz to 16 MHz. It is strongly recommended to measure the oscillation allowance (negative resistance) in the final target system (layout) to determine the optimum parameters for the oscillator operation. Please refer to the limits specified by the crystal supplier. When driven by an external clock signal it will accept the specified frequency range. Operation at lower input frequencies is possible but is verified by design only (not subject to production test).
Data Sheet
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V1.2, 2007-03
XC164KM Derivatives
Package and Reliability
5
Package and Reliability
In addition to the electrical parameters, the following information ensures proper integration of the XC164KM into the target system.
5.1
Packaging
These parameters describe the housing rather than the silicon. Package Outlines
Figure 16
PG-LQFP-64-4 (Plastic Green Low profile Quad Flat Package), valid for the -16F derivatives
Data Sheet
59
V1.2, 2007-03
XC164KM Derivatives
Package and Reliability
1.6 MAX.
1.4 0.05
0.1 0.05
0.15 +0.03 -0.06
0.6 0.15
H
0.5
0.2 -0.03
+0.07 2)
7.5
C
0.08
0.08 M A-B D C 64x 12
10 1)
0.2 A-B D 4x D 0.2 A-B D H 4x B
10 1)
A
64
1 Index Marking 1) Does not include plastic or metal protrusion of 0.25 max. per side 2) Does not include dambar protrusion of 0.08 max. per side
Figure 17
PG-TQFP-64-8 (Plastic Thin Quad Flat Package), valid for the -4F/8F derivatives
You can find all of our packages, sorts of packing and others in our Infineon Internet Page "Products": http://www.infineon.com/products Dimensions in mm. Table 18 Parameter PG-LQFP-64-4 Thermal resistance junction to case Thermal resistance junction to leads PG-TQFP-64-8 Thermal resistance junction to case Thermal resistance junction to leads
Data Sheet
Package Parameters Symbol Limit Values Min. Max. 8 23 K/W K/W - - Unit Notes
RJC RJL
- -
RJC RJL
- -
12
9 19
K/W K/W
60
7 MAX.
- -
V1.2, 2007-03
XC164KM Derivatives
Package and Reliability
5.2
Flash Memory Parameters
The data retention time of the XC164KM's Flash memory (i.e. the time after which stored data can still be retrieved) depends on the number of times the Flash memory has been erased and programmed. Table 19 Parameter Data retention time Flash Parameters Symbol Limit Values Min. Max. - - years 103 erase/program cycles 15 20 x 103 Unit Notes
tRET
Flash Erase Endurance NER
cycles Data retention time 5 years
Data Sheet
61
V1.2, 2007-03
www.infineon.com
B158-H8888-G1-X-7600
Published by Infineon Technologies AG

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